Source Themes

To address the issues of voltage mismatch, limited power extraction, and regulation losses in triple-well on-chip solar cells, this work implements a storage-free dual-channel EH system in standard 0.18-μ m CMOS technology. The system employs a per-port independent boosting architecture with post-boost parallel merging, effectively avoiding energy losses caused by MPP voltage mismatch in conventional designs. Meanwhile, a voltage regulation mechanism based on the load characteristics of the solar cell achieves stabilization without an LDO, enabling fast power control and adaptive power distribution, which better suits the requirements of storage-free EH. Experimental results show that the system maintains a stable 1.22-V output under varying illumination and load conditions; compared with a single-channel design, the voltage ripple is reduced from 102 to 21 mV, the load capacity is improved by 6.31%, and peak circuit and system efficiencies of 63.97% and 9.63% are achieved at 100 kLux, respectively. These results verify the proposed dual-channel EH system’s optimization in power extraction and voltage regulation, highlighting its potential for self-powered microsystems and hybrid energy architectures.

In summary, this structure offers an effective on-chip ESD protection solution for the reliability design of high-voltage industrial communication buses.

A RIS-loaded inductively fed FWD RFID tag antenna is proposed for PCstraceability in both metal-mounted and concrete-embedded scenarios.

This paper presents an ultra-low-power bootstrap-body-input transconductor with a tunable Gm range of 27–581 pA/V, achieving a 1200× reduction in transconductance and consuming only 0.88 nW at 0.8 V for biomedical filter applications.

This work presents a low-power CMOS AFE with adaptive dark current compensation and reconfigurable TIA, achieving 158.51dBΩ gain and 14.89fA/Hz noise for high-precision fiber temperature sensing.

This article proposed a dual-channel pseudo-differential AFE circuit using a 0.18 μ m CMOS process.

This DLL achieves 0.87ps phase offset and locks in 42 cycles using an improved phase detector. The 180nm CMOS design runs at 500MHz with 1.89mW power and 1.01ps jitter.

This brief presents an ultra-low-power HDR CMOS image sensor inspired by visual neuronal responses, achieving 88.96 dB dynamic range at 0.8 V with just 18.62 μW power consumption for IoT biomedical applications.

In this article, a bypass window SAR ADC structure based on multiple splits of the MSB capacitor is proposed for the characteristics of 12-lead ECG signals to minimize the power consumption.

This paper introduces a low-power SAR ADC with dual bypass windows, achieving 9.68nW at 0.6V for biomedical signals. It features cycle skipping and a dynamic comparator, enabling 9.26-bit ENOB with EMG/ECG/EEG compatibility.