Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

Abstract

This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

Ruihuang Wu

M.Sc.

My research interests include circuit design of delay loop lock.

Yuxuan Huang

M.Sc.

My research interests include circuit design of low-power reference.

Haoning Sun

Master’s Student

My research interests include circuit design of analog to digital converter for biomedical applications and noise shaping SAR ADC.

Kangkang Sun

PhD Student

My research interests include circuit design of analog to digital converter for biomedical applications and SAR ADC.

Xueting Pang

M.Sc.

My research interests include circuit design of temperature sensors.

Jingjing Liu

Associate Professor

My research interests include low-power smart micro-sensor integrated circuit design, image sensors, biomedical sensors, and energy harvesting circuits.