Abstract
This paper presents a low-power CMOS voltage reference (VR) based on a two-stage stacked diode-connected MOS transistor (SDMT) structure, implemented entirely with MOS transistors. The VR is designed using a standard 0.18 μm CMOS process and occupies an active area of 0.029 mm2, with all transistors operating in the subthreshold region. Post-layout simulations show that the reference voltage reaches 365 mV at 27 °C, while the power consumption is only 8.91 nW. The VR exhibits a temperature coefficient of 1.74 ppm/°C across a wide temperature range from −40 °C to 125 °C. In addition, it demonstrates a line sensitivity (LS) of 0.25 %/V over a supply voltage range of 0.7 V to 1.8 V, confirming its excellent stability and ultra-low-power performance for temperature sensor applications.
Publication
In 2026 IEEE International Symposium on Circuits and Systems (ISCAS), 2026

PhD Student
My research interests include circuit design of optical receivers and references.

PhD Student
My research interests include circuit design of analog front end for biomedical applications and sensor interfaces.

PhD Student
My research interests include circuit design of analog to digital converter for biomedical applications and SAR ADC.

PhD Student
My research interests include circuit design of image sensors and energy harvesting circuits.

PhD Student
My research interests include the design of solar cells and energy harvesting circuits.

Associate Professor
My research interests include low-power smart micro-sensor integrated circuit design, image sensors, biomedical sensors, and energy harvesting circuits.