
This paper proposes a high-energy-efficiency, direct-integration third-order passive noise-shaping (NS) successive approximation register analog-to-digital converter (SAR ADC) for biomedical applications. By directly sampling the residue voltage on the integrator and connecting the integration capacitors to the comparator through a charge-pump cascade, the proposed NS SAR ADC significantly reduces quantization-noise loss during the sampling/integration process, relaxes the gain requirement of the differential input pairs, lowers comparator power consumption, and enhances noise-shaping performance. The proposed NS SAR ADC is designed based on a standard 180nm CMOS technology. Under a 1.2V power supply, the ADC achieves 87.36 dB signal-to-noise-and-distortion ratio (SNDR) over a 55.6 kHz bandwidth at 1.78 MS/s while consuming only 9.67 μW. The corresponding Schreier figure-of-merit (FoM) is 184.96 dB and the Walden FoM is 4.6 fJ/conversion-step, offering an energy-efficient solution for ultra-low-power biomedical systems.