Article-Journal

This paper presents an ultra-low-power bootstrap-body-input transconductor with a tunable Gm range of 27–581 pA/V, achieving a 1200× reduction in transconductance and consuming only 0.88 nW at 0.8 V for biomedical filter applications.

This work presents a low-power CMOS AFE with adaptive dark current compensation and reconfigurable TIA, achieving 158.51dBΩ gain and 14.89fA/Hz noise for high-precision fiber temperature sensing.

This article proposed a dual-channel pseudo-differential AFE circuit using a 0.18 μ m CMOS process.

This DLL achieves 0.87ps phase offset and locks in 42 cycles using an improved phase detector. The 180nm CMOS design runs at 500MHz with 1.89mW power and 1.01ps jitter.

This brief presents an ultra-low-power HDR CMOS image sensor inspired by visual neuronal responses, achieving 88.96 dB dynamic range at 0.8 V with just 18.62 μW power consumption for IoT biomedical applications.

In this article, a bypass window SAR ADC structure based on multiple splits of the MSB capacitor is proposed for the characteristics of 12-lead ECG signals to minimize the power consumption.

This paper introduces a low-power SAR ADC with dual bypass windows, achieving 9.68nW at 0.6V for biomedical signals. It features cycle skipping and a dynamic comparator, enabling 9.26-bit ENOB with EMG/ECG/EEG compatibility.

This brief proposes a subthreshold CMOS CR circuit based on a modified self-biased β -multiplier implemented in a standard 0.18-μ m CMOS process for ultralow-power applications.

This paper introduces a pseudo two-stage pipeline SDPF processor, which enhances the performance of SDPF RISC-V processors by reducing CPI in the serial data path through simulated pipeline structures, which achieves improved performance while maintaining low power and area overheads.

This work proposes a CIS capable of simultaneous imaging and energy harvesting without the need for additional p-n junctions in the pixel array.